----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:16:29 03/09/2012 
-- Design Name: 
-- Module Name:    totaal_uart_rx - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--library WORK;
--use work.overflow_pack.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity totaal_uart is
	port(
--RX			
					 RX_serial_in : in std_logic;
					  RX_data_out : out std_logic_vector(7 downto 0);
				  RX_read_buffer : in std_logic;
				 RX_reset_buffer : in std_logic;
				 --RX_en_16_x_baud : in std_logic;
		RX_buffer_data_present : out std_logic;
				  RX_buffer_full : out std_logic;
			RX_buffer_half_full : out std_logic;
--TX 
						TX_data_in : in std_logic_vector(7 downto 0);
             TX_write_buffer : in std_logic;
             TX_reset_buffer : in std_logic;
             --TX_en_16_x_baud : in std_logic;
               TX_serial_out : out std_logic;
               TX_buffer_full : out std_logic;
         TX_buffer_half_full : out std_logic;
							    clk : in std_logic);
end totaal_uart;

architecture Behavioral of totaal_uart is

component uart_rx is
    Port (            serial_in : in std_logic;
                       data_out : out std_logic_vector(7 downto 0);
                    read_buffer : in std_logic;
                   reset_buffer : in std_logic;
                   en_16_x_baud : in std_logic;
            buffer_data_present : out std_logic;
                    buffer_full : out std_logic;
               buffer_half_full : out std_logic;
                            clk : in std_logic);
    end component;
	 
component uart_tx is
    Port (            	data_in : in std_logic_vector(7 downto 0);
						 write_buffer : in std_logic;
						 reset_buffer : in std_logic;
						 en_16_x_baud : in std_logic;
							serial_out : out std_logic;
						  buffer_full : out std_logic;
					buffer_half_full : out std_logic;
									 clk : in std_logic);
    end component;
	 
component uartklok is
    Port ( clk : in  STD_LOGIC;
           uart_klok : out  STD_LOGIC);
end component;

component overflow is
		Port ( 	clk, baud_clk, data_1, data_16 : in  STD_LOGIC;
					reset_RX : out  STD_LOGIC);
end component;

signal clock_gedeeld : std_logic;
signal S_RX_buffer_data_present	: std_logic;
signal S_RX_buffer_full : std_logic;
signal S_RX_reset_buffer : std_logic;
signal reset_RX : std_logic;

begin

RX : uart_rx PORT MAP(
		serial_in => RX_serial_in,
		data_out => RX_data_out,
		read_buffer => RX_read_buffer,
		reset_buffer => S_RX_reset_buffer,
		en_16_x_baud => clock_gedeeld,
		buffer_data_present => S_RX_buffer_data_present,
		buffer_full => S_RX_buffer_full,
		buffer_half_full => RX_buffer_half_full,
		clk => clk
	);

TX: uart_tx PORT MAP(
		data_in => TX_data_in,
		write_buffer => TX_write_buffer,
		reset_buffer => TX_reset_buffer,
		en_16_x_baud => clock_gedeeld,
		serial_out => TX_serial_out,
		buffer_full => TX_buffer_full,
		buffer_half_full => TX_buffer_half_full,
		clk => clk
	);

klokdeler: uartklok PORT MAP(
		clk => clk,
		uart_klok => clock_gedeeld
	);

	Inst_overflow: overflow PORT MAP(
		clk => clk,
		baud_clk => clock_gedeeld,
		data_1 => S_RX_buffer_data_present,
		data_16 => S_RX_buffer_full,
		reset_RX => reset_RX
	);
	RX_buffer_data_present <= S_RX_buffer_data_present;
	RX_buffer_full <= S_RX_buffer_full;
	S_RX_reset_buffer <= reset_RX OR RX_reset_buffer;
	
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

package UART_PACK is

component totaal_uart is 
		port(
--RX			
					 RX_serial_in : in std_logic;
					  RX_data_out : out std_logic_vector(7 downto 0);
				  RX_read_buffer : in std_logic;
				 RX_reset_buffer : in std_logic;
				 --RX_en_16_x_baud : in std_logic;
		RX_buffer_data_present : out std_logic;
				  RX_buffer_full : out std_logic;
			RX_buffer_half_full : out std_logic;
--TX 
						TX_data_in : in std_logic_vector(7 downto 0);
             TX_write_buffer : in std_logic;
             TX_reset_buffer : in std_logic;
             --TX_en_16_x_baud : in std_logic;
               TX_serial_out : out std_logic;
               TX_buffer_full : out std_logic;
         TX_buffer_half_full : out std_logic;
							    clk : in std_logic);
end component; 

end UART_PACK;